ALT + + Schriftgröße anpassen
ALT + / Kontrast anpassen
ALT + M Hauptnavigation
ALT + Y Socials
ALT + W Studiengang wählen
ALT + K Homenavigation
ALT + G Bildwechsel
ALT + S Übersicht
ALT + P Funktionsleiste
ALT + O Suche
ALT + N Linke Navigation
ALT + C Inhalt
ALT + Q Quicklinks
ESC Alles zurücksetzen
X
A - keyboard accessible X
A
T
Forschung am E&D

Veröffentlichungen, Publications

 

2022

J. Scheible:
Optimized is Not Always Optimal - The Dilemma of Analog Design Automation; (invited paper), ISPD 2022, Int. Symposium on Physical Design, Virtual Event, Canada, 27.-30.03.2022, pp. 151-158, ACM ISBN 978-1-4503-9210-5/22/03, DOI, PDF.


 

2021

D. Marolt, J. Scheible, G. Jerke, V. Marolt:
The Essential Role of Procedural Approaches in Electronic Design Automation; SMACD 2021, Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 19.-22.07.2021, VDE, pp. 1-6, (invited paper), ISBN 978-3-8007-5588-2, URL.

M. Schweikardt, J. Scheible:
Improvement of Simulation-Based Analog Circuit Sizing using Design-Space Transformation; SMACD 2021, Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 19.-22.07.2021, VDE, pp. 1-4, (invited paper), ISBN 978-3-8007-5588-2, URL.

Y. Uhlmann, M. Essich, M. Schweikardt, J. Scheible, C. Curio:
Machine Learning Based Procedural Circuit Sizing and DC Operating Point Prediction; SMACD 2021, Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 19.-22.07.2021, VDE, pp. 1-4, ISBN 978-3-8007-5588-2, URL.

D. Marolt:
SWARM: A Novel Methodology for Integrrated Circuit Layout Automation Based on Principles of Self-Organization; Fortschritt-Berichte VDI, Reihe 20, Nr. 475, VDI-Verlag 2020, 256 Seiten, ISBN 978-3-18-347520-9.


 

2020

J. Lienig, J. Scheible:
Fundamentals of Layout Design for Electronic Circuits; 2020, 306 pages, Springer International Publishing, ISBN 978-3-030-39283-3, DOIInfos und weitere Materialien zu diesem Lehrbuch.


A. Hald:
Methoden zur Analyse parasitärer elektrostatischer Effekte in mikroelektromechanischen Systemen; Dissertation, Fortschritt-Berichte VDI, Reihe 20, Nr. 473, VDI-Verlag 2020, 176 Seiten, ISBN 978-3-18-347320-5.


H. Habal, D. Tsonev, M. Schweikardt:
Compact Models for Initial MOSFET Sizing Based on Higher-order Artificial Neural Networks; Proc. of the 2020 ACM/IEEE Workshop on Machine Learning for CAD (MLCAD '20), Iceland, 11/2020, pp. 111–116, DOI.


 

2019

A. Hald, R. Wolf, J. Seelhorst, J. Scheible, J. Lienig, S. Tibus, M. Schwarz:
Parasitic Extraction Methodology for MEMS Sensors with Active Devices; 16th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 15.-18.07.2019, ISBN 978-1-7281-1201-5/19, pp. 221-224, DOI.


M. Schweikardt, Y. Uhlmann, F. Leber, J. Scheible, H. Habal:
A Generic Procedural Generator for Sizing of Analog Integrated Circuits; Proc. of the 15th Conf. on Ph.D. Research in Microelectronics and Electronics (PRIME 2019), Lausanne, Switzerland, 15.-18.07.2019, ISBN 978-1-7281-3549-6, pp. 17-20, DOI


J. Scheible, D. Marolt, M. Schweikardt, H. Habal:
Optimiert ist nicht immer optimal: Automatisierung des Entwurfs analoger ICs - Teil 1; Elektronik, (06) 2019, ISSN: 0013-5658, pp. 46-50, elektroniknet.de: URL, PDF.


J. Scheible, D. Marolt, M. Schweikardt, H. Habal:
Optimiert ist nicht immer optimal: Automatisierung des Entwurfs analoger ICs - Teil 2; Elektronik, (08) 2019, ISSN: 0013-5658, pp. 32-37. elektroniknet.de: URL,PDF.


A. Hald, H. Marquardt, P. Herzogenrath, J. Scheible, J. Lienig, J. Seelhorst:
Full Custom MEMS Design: 2.5D Fabrication-Process Simulation for 3D Field-Solver-Based Circuit Extraction; IEEE Sensors Journal, Vol. 19, No. 14, 2019, ISSN: 1558-1748, pp. 5710-5717, DOI.


D. Marolt:
Layout automation in analog IC design with formalized and nonformalized expert knowledge; Dissertation, Online Publikationen der Universität Stuttgart (OPUS); DOI.


 

2018

S. Bigalke, J. Lienig, G. Jerke, J. Scheible, R. Jancke:
The Need and Opportunities of Electromigration-Aware Integrated Circuit Design; Proc. of the IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD '18), San Diego, CA, USA, 05.-08.11.2018, invited paper, DOI ,PDF.


F. Leber, J. Scheible:
A Procedural Approach to Automate the Manual Design Process in Analog Integrated Circuit Design; ANALOG 2018, 16th GMM/ITG-Symposium, GMM-Fachbericht 91, Munich/Neubiberg, Germany, 12.-14.09.2018, pp. 175-180, PDF, URL.


V. Borisov, J. Scheible:
Lithography Hotspots Detection Using Deep Learning; Proc. of the 15th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018), Prague, Czech Republic, 02.-05.07.2018, pp. 145-148, DOI.


V. Borisov, J. Scheible:
Research on Data Augmentation for Lithography Hotspot Detection Using Deep Learning; Proc. SPIE 10775, 34th European Mask and Lithography Conference (EMLC 2018), 107751A (19 Sep. 2018); Grenoble, France, 18.-20.06.2018, DOI.


A. Hald, P. Herzogenrath, J. Scheible, J. Lienig, J. Seelhorst, P. Brandl:
Full custom MEMS design: A new method for the analysis of motion-dependent parasitics; Integration, the VLSI Journal 63 (2018), Elsevier, pp. 362-372, DOI, free download.


F. Leber, P. Lamprecht, J. Scheible:
Eine domänenspezifische Sprache zur Automatisierung des Analogdesigns von Sourceschaltungen; 57. MPC-Workshop, Albstadt-Sigmaringen, Germany, 17.02.2017, (Vortrag ohne Paper).


M. Thoma, D. Marolt, J. Scheible:
Entwurf kontextbasierter PCells für Hochfrequenzanwendungen in modernen CMOS-Technologien; 58. MPC-Workshop, Reutlingen, Germany, 07.07.2017, ISSN 1868-9221, pp. 33-40, URL, Best Paper Award.


 

2017

A. Gerlach, T. Rosahl, F.-T. Eitrich, J. Scheible:
A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example; Conf. for Design and Test in Europe, DATE 2017, 27.-31.03.2017, Lausanne, Switzerland, pp. 898-901. PDF, DOI


A. Hald, J. Seelhorst, P. Herzogenrath, J. Scheible, J. Lienig:
A New Method for the Analysis of Movement Dependent Parasitics in Full Custom Designed MEMS Sensors; Proc. of the 14th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2017), Giardini Naxos - Taormina, Italy, 12.-15.06.2017, ISBN 978-1-5090-5051-2. PDF, EDA Competition Award.


V. Borisov, K. Langner, J. Scheible, B. Prautsch:
A Novel Approach for Automatic Common-Centroid Pattern Generation; Proc. of the 14th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2017), Giardini Naxos - Taormina, Italy, 12.-15.06.2017. PDF


K. Langner, J. Scheible:
Formal Verification of a Transistor PCell; Proc. of the 13th Conf. on Ph.D. Research in Microelectronics and Electronics (PRIME 2017), Giardini Naxos - Taormina, Italy, 12.-15.06.2017, ISBN 978-1-5090-6507-3, pp. 205-208. PDF


F. Leber, J. Scheible:
Eine domänenspezifische Sprache für die prozedurale Dimensionierung im analogen IC Entwurf; Tagungsband "Informatics Inside 2017", Hochschule Reutlingen, 10.05.2017, ISBN 978-3-00-056455-0, pp. 121-122. PDF,Tagungsband.


R. Eißler, J. Scheible:
Datenbankgestützte Generierung von Rulefiles für MEMS-Fertigungsprozesse; Tagungsband "Informatics Inside 2017", Hochschule Reutlingen, 10.05.2017, ISBN 978-3-00-056455-0, pp. 123-124. PDF, Tagungsband.


F. Leber, J. Scheible:
SKILL Application Manager (SAM) - Simplify Your Software Development in Virtuoso; Proc. of Cadence User Conference "CDNLive EMEA 2017", München, 15.-17.05.2017, Beitrag AC12 (Academic Track), PDF, Proceedings,Best Presentation Award.


 

2016

A. Hald, J. Seelhorst, M. Reimann, J. Scheible, J. Lienig:
A Novel Polygon-Based Circuit Extraction Algorithm for Full Custom Designed MEMS Sensors; Proc. of the 13th Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2016), Lisbon, Portugal, 27.-30.06.2016. PDF, DOI, EDA Competition Award


D. Marolt, J. Scheible, G. Jerke, V. Marolt:
A Self-organization Approach for Layout Floorplanning Problems in Analog IC Design; Proc. of the 12th Conf. on Ph.D. Research in Microelectronics and Electronics (PRIME 2016), Lisbon, Portugal, 27.-30.06.2016. PDF, DOI


M. Greif, D. Marolt, J. Scheible:
gPCDS: An Interactive Tool for Creating Schematic Module Generators in Analog IC Design; Proc. of the 12th Conf. on Ph.D. Research in Microelectronics and Electronics (PRIME 2016), Lisbon, Portugal, 27.-30.06.2016. PDF, DOI


D. Marolt, T. Burdick, G. Jerke, P. Herth, V. Marolt, J. Scheible:
HIPE: Hierarchical Instance Parameter Editing of Parameterized Modules in Analog IC Design; Proc. of edaWorkshop 16, 11.-12.05.2016, Hannover, ISBN 978-3-86460-453-9, pp. 18-23.


D. Marolt, J. Scheible, G. Jerke, V. Marolt:
SWARM: A Multi-agent System for Layout Automation in Analog Integrated Circuit Design; Proc. of 10th KES Int Conf., KES-AMSTA 2016, Puerto de la Cruz, Tenerife, Spain, June 2016, in G. Jezic et al. (eds.): "Agent and Multi-Agent Systems: Technology and Applications, Smart Innovation, Systems and Technologies 58", pp. 15-31, Springer, ISBN: 978-3-319-39882-2, Free Download.


D. Marolt, J. Scheible, G. Jerke, V. Marolt:
SWARM: A self-organization approach for layout automation in analog IC design; Int. Journal of Electronics and Electrical Engineering (IJEEE), 2016, Vol. 4 (5), pp. 374-385. DOI


D. Marolt, J. Scheible, G. Jerke, V. Marolt:
Analog layout automation via self-organization: Enhancing the novel SWARM approach; Proc. of the IEEE 7th Latin American Symposium on Circuits and Systems (LASCAS 2016), 28.02.2016 - 02.03.2016, Florianopolis, Brasilien, pp. 55-58, http://dx.doi.org/10.1109/LASCAS.2016.7451008.


 

2015

C.C. Jung, J. Scheible:
Heat Generation in Bond Wires; IEEE Transactions on Components, Packaging and Manufacturing Technology, Okt. 2015, Vol. 5 (10), ISSN: 2156-3950, pp. 1465-1476, http://dx.doi.org/10.1109/TCPMT.2015.2429743.


C.C. Jung, C. Silber, J. Scheible:
Bond Wire Design with the Bond Calculator; 8. GMM/ITG/GI-Fachtagung "Zuverlässigkeit und Entwurf" (ZuE 2015), 21.-23.09.2015, Siegen, GMM-Fachbericht 83, VDE-Verlag, ISBN 978-3-8007-4071-0, pp. 30-35.


D. Marolt, J. Scheible, G. Jerke, V. Marolt:
SWARM: A Self-organization Approach for Layout Automation in Analog IC Design; 8th Int. Conf. on Computer and Electrical Engineering (ICCEE 2015), 12.-13.10.2015, Paris, Frankreich. Excellent Paper Award.


J. Scheible, J. Lienig:
Automation of Analog IC Layout – Challenges and Solutions; Proc. of Int. Symp. on Physical Design (ISPD'15), 29.03.-1.4.2015, Monterey, CA, USA, pp. 33-40, (eingeladen), http://dx.doi.org/10.1145/2717764.2717781.


M. Greif, D. Marolt, J. Scheible:
Konzeptstudie eines durchgängig auf parametrisierten Modulgeneratoren basierenden Entwurfsflusses für Analogdesign; 53. MPC-Workshop, Esslingen, Germany, 06.02.2015, ISSN 1868-9221, pp. 23-30, http://www.mpc.belwue.de/Public/WorkshopBand53.


D. Marolt, J. Scheible:
CAPABLE: A Constraint-Administered PCell-Applying Blocklevel Layout Engine;
54. MPC-Workshop, Ulm, Germany, 10.07.2015, ISSN 1868-9221, pp. 49-59, http://www.mpc.belwue.de/Public/WorkshopBand54.


C.C. Jung, C. Silber, J. Scheible:
Temperature Profiles Along Bonding Wires, Revealed by the Bond Calculator, a New Thermo-Electrical Simulation Tool; IEEE Int. Conf. on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2015), 19.-22.04.2015, Budapest, Ungarn, pp. 1-9, http://dx.doi.org/10.1109/EuroSimE.2015.7103148.


A. Gerlach, J. Scheible, T. Rosahl, F.-T. Eitrich:
A Generic Topology Selection Method for Analog Circuits Demonstrated on the OTA Example; 11th Conf. on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), 29.06.-02.07.2015, Glasgow, UK, pp. 77-80, dx/doi/org/10.1109/PRIME.2015.7251338.


 

2014

D. Marolt, M. Greif, J. Scheible, G. Jerke:
PCDS: A New Approach for the Development of Circuit Generators in Analog IC Design; 22nd Austrian Workshop on Microelectronics (Austrochip), Oct. 2014, pp. 1-6. http://dx.doi.org/10.1109/Austrochip.2014.6946310.


D. Marolt, J. Scheible, G. Jerke:
A Distinct Bottom-Up Paradigm to Tackle the Layout Automation Gap in Analog IC Design; 51. Design Automation Conference (DAC 2014), San Francisco, 1.-5.6.2014, Postersession "Work in Progress".


A. Gerlach, M. Junge, J. Scheible, T. Rosahl:
Optimierte, wiederverwendbare OTA-Schaltungen für moderne Power BiCMOS-Technologien; 52. MPC-Workshop, Künzelsau, Germany, 11.07.2014, ISSN 1868-9221, pp. 21-26, http://www.mpc.belwue.de/Public/WorkshopBand52.


J. Scheible, I. Bausch-Gall, C. Deatcu (Hrsg.):
ASIM-Workshop STS/GMMS 2014 - Tagungsband; ASIM-Workshop STS/GMMS 2014, 20.-21.02.2014, ARGESIM / ASIM Wien – Hochschule Reutlingen, ISBN 978-3-901608-42-1, 268 Seiten.


A. Gerlach, M. Junge, J. Scheible:
Universelle OTA-Testbench; ASIM-Workshop STS/GMMS 2014, 20.-21.02.2014, ARGESIM / ASIM Wien – Hochschule Reutlingen, ISBN 978-3-901608-42-1, pp. 83-87.


C.C. Jung, C. Silber, J. Scheible:
Thermische Simulation von Bonddrähten in verpackten Chips unter Berücksichtigung der Draht-Package-Interaktion; ASIM-Workshop STS/GMMS 2014, 20.-21.02.2014, ARGESIM / ASIM Wien – Hochschule Reutlingen, ISBN 978-3-901608-42-1, pp. 37-47.


 

2013

J. Scheible:
A Novel Collegiate Chip Design Laboratory in a Novel Academic Institution; Proceedings of CDNLive EMEA 2013, 6.-8.5.2013, Munich, Germany, ISSN: 2114-3676, Beitrag Nr. AC11, 21 Seiten.


D. Marolt, J. Scheible, G. Jerke:
A practical layout module pcell concept for analog IC design; Proceedings of CDNLive EMEA 2013, 6.-8.5.2013, Munich, Germany, ISSN: 2114-3676, Beitrag Nr. CUS01, 6 Seiten.


J. Scheible:
Constraint driven Design - Eine Wegskizze zum analogen Designflow der nächsten Generation; In G. Forster (Hrsg.) "Mikroelektronik", Hochschule Ulm, Juli 2013, ISBN 978-3-9810998-6-7, pp. 31-36.


 

2012

A. Gerlach, D. Marolt, J. Scheible:
Der Bond-Rechner - Ein Werkzeug zur Dimensionierung von Bonddrähten; 6. GMM/GI/ITG-Fachtagung ZuE 2012, Zuverlässigkeit und Entwurf, Bremen, Germany, 25.-27.09.2012, ISSN 1432-3419, pp. 35-38.


S. Gohm, D. Marolt, J. Scheible:
Parametrisierte Layout-Module für den analogen IC-Entwurf; 48. MPC-Workshop, Aalen, Germany, 06.07.2012, ISSN 1868-9221, pp. 57-63.


D. Marolt, J. Scheible:
Parameterized Cells in Analog IC Design; Design Automation and Test in Europe, DATE 12, Dresden, Germany, 12.-16.03.2012.


 

2011

J. Scheible:
Electronic Design Automation; Proceedings NPIE/Stuttgart/Reutlingen Joint Workshop on Emerging Technology for Power Electronics, National Chiao Tung University, Hsinchu, Taiwan, 27.06.2011, pp. 97-109.


D. Marolt, J. Scheible:
The Application of Layout Module Generators upon Circuit Structure Recognition; Cadence CDNLive EMEA User Conference 2011, München, Germany, 03.-05.05.2011, Paper AC13. URL.